1. Field of the Invention
The present invention relates to data processors that perform pipeline processing by means of internal bus organizations that provide miniaturization of processors and high-speed operation and to data processors that have instruction codes that provide miniaturization of programs.
2. Description of the Related Art
Existing data processors are organized in such a way that the internal arithmetic/logic unit is connected to registers for retaining data through two or more internal buses in order to reduce operation time. In a data processor having two internal buses, an operation between two registers is performed using two machine cycles. During the first cycle the contents of the registers are read into the two buses and input into the arithmetic/logic unit. During the second cycle the result of the operation performed by the arithmetic/logic unit is output into either one of the two buses and written into a register.
In a data processor having three internal buses, an operation between two registers can be performed in one machine cycle. During the first cycle the contents of the registers are read into the first and second buses and input into the arithmetic/logic unit. The result of the operation is output into the third bus during the second cycle. The first and second buses are related to the third bus as a pipeline system. While the result of the operation is output into the third bus, the data for the next operation are output into the first and second buses. Therefore, in a data processor having three buses, one operation between two registers can be performed in one machine cycle.
While data processors having three internal buses make high-speed operation possible, each register has to be connected to the arithmetic-logic unit through three internal buses, and the hardware tends to expand. Therefore, data processors having three internal buses are not fit to be built into low-cost oriented equipment. On the other hand, while existing data processors having two internal buses downsize the hardware, an operations between registers or a data transfer between a register and the memory is hard to be performed in one machine cycle.
Some of prior data processors limit the objects of operations to data storage memory. In this type of data processors, an operation is performed following an instruction composed of one operation code and two operand addresses.
Some of prior data processors have a special register called accumulator and other registers, and the objects of main operations include the accumulator. In this type of data processors, an operation is performed following an instruction composed of one operation code and one operand code designating a memory address or a register other than the accumulator.
There are also data processors having general-purpose registers such that any pair of them can be the objects of several operations, and an instruction is composed of an operation code and two operand codes designating two registers.
However, in the above data processors having the memory as the sole objects of operations, an instruction word length becomes large, since an instruction requires two operand address fields. Therefore, the size of a program written for this type of data processors is generally large.
In the above data processors having an accumulator, an instruction word length is small, since an instruction has only one operand address. However, the data transfers between the accumulator and other registers or the memory are frequently required, since the objects of main operations include the accumulator. As a result, a program size is generally large, and the processing speed for executing a program tends to be slow.
On the other hand, in data processors having general-purpose registers, the number of instructions in a program can be reduced, since any pair of general-purpose registers can be the objects of operations. Also, an instruction word length is comparatively small, since the operand of an instruction is register-designating codes, which are shorter than for memory addresses. However, the instruction word length of an operation between two registers can not be made smaller than in data processors having an accumulator for the following reason.
For example, if a data processor has 8 general-purpose registers, then the code designating one register requires at least three bits, and the instruction for an operation between two registers requires 6-bit register fields. If, in this case, the instruction word length is 8 bits, then the remaining two bits facilitate only four kinds of instructions, which are less than required. Therefore, in practice, an instruction word length is made 16 bits. Therefore, it is hard for data processors having general-purpose registers to perform a number of different kinds of operations by means of instructions having a small word length.